Community Newsletter: May 2015
IN THIS ISSUE:
- Message from the Chair
Looking forward to new frontiers
- Accellera at the Design Automation Conference
Join us at our annual Breakfast & Panel Discussion and the System Level Power Workshop
- Spotlight: UVM in SystemC
Accellera’s UVM in SystemC Standardization: Going Universal for ESL
- DVCon Has Gone Global
Ramping up for DVCon India and DVCon Europe
- Accellera in the News
Accellera Systems Initiative UVM 1.2 proceeds to IEEE standardization
- Public Review Extended
SystemC Synthesizable Subset Version 1.4 review extended to July 13
- Upcoming Event
SystemC Japan to be held in June
I’d like to extend a warm welcome to our three new members: AMIQ, CVC and Vayavya Labs. We are happy to have them join our efforts and look forward to collaborating with them. Our members currently represent more than 11 countries, giving a voice to standards development worldwide.
Accellera members continue to work together to evolve standards such as SystemC, SystemVerilog AMS, UVM and IP-XACT, as well as supporting the many IEEE standards that originated in Accellera. We look to new frontiers such as Portable Stimulus and Transaction Level Protocols to determine how standards development in these areas can benefit the industry. As exciting new technologies emerge in this new era of IoT, Accellera members across the globe will be teaming to develop standards that will help accelerate development.
At Accellera, our mission is to provide a platform in which the electronics industry can collaborate to innovate and deliver global standards that improve design and verification productivity for electronics products. It is evident by the many discussions and presentations on the agenda at the upcoming Design Automation Conference that tremendous opportunities abound.
I look forward to seeing you at DAC next month.
Shishpal Rawat, Accellera Systems Initiative Chair
There's something for everyone at DAC this year. If you're on a budget and would like to attend our events as well as the keynotes, DAC Pavilion events, Cocktails and Conversation receptions, Designer Track and IP Poster Sessions, Skytalks and 3 days of exhibits, we encourage you to register for "I Love DAC," which provides the opportunity to attend these events and many others for free. Deadline to register is May 19th.
Accellera Breakfast and Panel Discussion
"Design and Verification Standards in the Era of IoT"
Tuesday, June 9, 2015
7:30am - 9:00am
Moscone Center, Room 220
The era of Internet of Things (IoT) will usher increased use of communication and other protocols for rapid development and interconnect of new devices. These projects will be run on shrinking timelines with more globalized teams, increasing the need for design and verification standards. I2C, MIPI, WiFi and other protocols are already implemented using SystemC, SystemVerilog, UPF, UVM and other standards originated by Accellera and globalized in the IEEE. By working more closely together, the protocol working groups and the design and verification working groups can provide key technology to accelerate development in the era of IoT.
The Accellera breakfast panel brings together senior technologists from the IoT community to discuss the current status and future needs for standards cooperation. We welcome you to join this lively discussion and get your creative minds running before you head into your IoT, automotive, and other sessions at DAC 2015.
Moderator: John Blyler, Editorial Director, Embedded IoT Systems, Portland, OR
System Level Power Workshop
Tuesday, June 9 2015
1:15pm - 4:30pm
Moscone Center, Room 206
Low power remains a hot topic for designers, verification engineers, IP developers and tool providers. In particular, interoperability among tools and IP remains a big concern for the engineers dealing with low power issues. In the past decade, standards have played an important role in building a design and verification environment that addresses interoperability issues. Collectively, as the industry learns how to solve current issues, it uncovers that there are more issues to solve at the system level in order to keep up with the growing complexity of designs and processes. Besides agreeing on the definition of system level, creation of power models and their suitability at different levels of abstraction for appropriate analysis remains a challenge.
With this in mind, a System Level Power workshop will be held at DAC. The workshop is co-organized and sponsored by the IEEE Design Automation Standards Committee (DASC), Si2 and Accellera.
UVM-SystemC development was initiated in a European project as part of the 7th Framework Programme, Verification for heterogeneous Reliable Design and Integration (VERDI), with the objective to develop a unified system-level verification methodology for heterogeneous systems. Much progress has been made since June 2014 when VERDI contributed the UVM-SystemC language reference manual (LRM) and reference implementation to Accellera for continued development. For more information about UVM-SystemC progress, read the new article, "Accellera’s UVM in SystemC Standardization: Going Universal for ESL." To get involved in the discussions, please visit the SystemC community and forum pages. To learn more, please view the video tutorial presented at DVCon US and view a technical paper by Martin Barnasconi, SystemC AMS Working Group chair.
Article: Accellera’s UVM in SystemC Standardization: Going Universal for ESL >
Video Tutorial: SystemC Standardization Update Including UVM for SystemC >
Technical Paper: Advancing system-level verification using UVM in SystemC >
The 27th annual DVCon US held in March continued its reign as the premier conference for discussion of the functional design and verification of electronic systems. The conference concluded this year with record overall attendance numbers and a sold out exhibit floor. DVCon is in its second year of extending the rich technical program attendees have come to expect in the US to Europe and India.
DVCon India will be held September 10-11, 2015 in Bangalore. The conference has 2 parallel tracks:
- ESL Track: SystemC-related topics such as Pre-Si software development and debug using virtual prototypes of electronic systems and SoCs, architectural exploration, power and performance analysis for use on cases, high-level synthesis, model interoperable standards, etc.
- DV Track: Design & Verification languages, methodologies based on SystemVerilog, Verilog, UVM and technologies such as formal verification, hardware acceleration, emulation and prototyping, simulation, etc.
DVCon Europe will be held November 11-12 in Munich, Germany.
The run up to DVCon Europe has started in earnest. Building on the technical excellence of the 2014 program, we are already seeing high caliber paper and tutorial submissions for this year's event. It is clear that there is a high demand in Europe for this exhibition, so we have almost doubled the size of the show floor over last year and again expect a sold out show. If you want exposure in Europe, this is the place to be!
Call for Tutorials submission deadline is June 1.
Accellera Systems Initiative UVM 1.2 Proceeds to IEEE Standardization
In March, Accellera announced that the Accellera Universal Verification Methodology (UVM) 1.2 standard is proceeding to IEEE standardization. Already proven in the electronics industry, the UVM standard will benefit from worldwide recognition, formalization, and this first step toward being language agnostic as a result of the formation of the P1800.2 working group. This work extends the ability of the UVM standard to improve interoperability and reduce the cost of IP development and reuse for each new electronics project.
The deadline for public review and comment on the SystemC Synthesizable Subset Version 1.4 has been extended to July 13, 2015. The document can be downloaded here. For more information and to submit feedback, please visit the working group's public forum.
June 19, 2015
Shinyokohama Kokusai Hotel
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Copyright 2015 Accellera Systems Initiative