IP Security Assurance Working Group


The Accellera board formed a Working Group to define an IP Security Assurance Specification. The Working Group will provide a security assurance standard for hardware IP and its associated components to address security risks when integrated into embedded systems.

This Working Group is now dormant as the Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0 has been contributed to the IEEE for the development of the P3164 draft standard.


Currently there is no single standard that addresses security assurance in the development and delivery of intellectual property (IP) to Silicon integrators. With this new standard, user companies will have high confidence that IPs have addressed security concerns at the integration level.

With a single specification, user companies will be able to select the best tool(s) from competing vendors to achieve the best results for their products.

The initial scope for the Working Group is to define an automated systematic approach that can be consistently supported across multiple target implementations. The WG will focus on existing standards that pertain to IP specification, design, verification and integration where security risk is a concern, as well as known security concerns that have been identified by either industry experience or security researchers


There is a certain level of risk when integrating third-party IP (3PIP) into Silicon. The risk stems from unknown behaviors that may occur once integrated, which could result as an exploitable vulnerability. Even if the source was provided, these unknowns may still exist since integrators typically treat 3PIP as "black-box" technology. Silicon providers need a security assurance standard for acceptance before integrating 3PIP in order to minimize risk in their products. High-quality Silicon products are only such when they are built from high-quality IPs. 

Join this Working Group

This Working Group is now dormant. For more information contact us.