To support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry, Accellera hosts and supports numerous events throughout the year.

UVM-AMS Proposed Working Group Kick Off Meeting

Wednesday, May 22
10:00am-4:00pm CEST
NXP Semiconductors
Schatzbogen 7, 81829
Munich, Germany

Accellera has formed a Proposed Working Group (PWG) to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard.

“Our ambition is to apply UVM for both digital and analog/mixed signal verification,” stated Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog and mixed-signal extensions to UVM and determine if a path to standardization is feasible. We encourage all interested companies to join our initial PWG meeting and provide input for standardization.”

The initial meeting will cover presentations on industry best practices, discuss scope and requirements, and explore directions for standardization.  For more information on the UVM-AMS PWG visit here. (Registration is now closed)

DAC 2019DAC 2019

June 2-6, 2019
Las Vegas Convention Center
Las Vegas, NV

DAC Luncheon and Panel of Industry Experts Addressing IP Security Assurance Issues

Monday, June 3
Room N246, Las Vegas Convention Center

We invite you to join us at DAC for a brief update on Accellera activities from our Chair Lu Dai, followed by an informative and thought-provoking panel addressing IP security issues. Security is as important to electronic systems as functionality is. This statement is bold, but it is reality. While the need is obvious in mission-critical applications such as automotive, communications, defense, industrial, and medical, no one wants to see their cell phone compromised or have their robotic lawnmower run amok. Therefore, security principles must exist in all levels of these systems, must be addressed at all phases of product development, and must be sustained throughout the product lifecycle.

The experts seated on the Accellera panel at DAC will discuss the challenges and approaches needed to address security. Among the topics we will explore are:

  • Responsibilities of system architects, program managers, and engineers
  • Requirements for a trusted development process across the design chain
  • Assessing security levels of IP blocks and sustaining security through SoC integration
  • Sustainability of security for deployed products as new threats arise

Panelists include: Lei Poo, Analog Devices; Serge Leef, DARPA; Brent Sherman, Intel and IPSA Working Group Chair; Andrew Dauman, Tortuga Logic. The panel will be moderated by Adam Sherer, Cadence and IPSA Working Group Secretary.

Please join us for this lively discussion as we address a broad topic impacting every electronic system. The Accellera-sponsored luncheon is free to DAC attendees, but registration is required.

DAC Designer Track Session: SystemC in the Real World

Wednesday, June 5
Room N260, Las Vegas Convention Center

SystemC has been widely used for almost two decades as the medium of choice for building abstract, transaction-level models. Architects and designers use these high-level models for architectural exploration and coarse-grained performance or throughput modeling. In production flows it’s important to incorporate the information contained in those abstract models into downstream, concrete portions of the flow. Connecting transaction-level modeling flows with RTL flows has long been ignored. In this DAC session, interactions between the two will be explored. How the two modeling environments can work together, each complimenting the other, to form flows that span the entire lifetime of a design from architectural exploration to coverage closure and timing closure will be discussed.

Registration with the Design Automation Conference is required to attend this presentation. Find out more about this session >

DVCon India 2019DVCon India

September 25-26, 2019
The Leela Palace Bengaluru
Bengaluru, India

Call for Papers | Proposal deadline extended to May 17, 2019
Call for Tutorials | Proposals due May 27, 2019

DVCon Europe 2019DVCon Europe

October 29-30, 2019
Holiday Inn Munich City Centre
Munich, Germany

SystemC Evolution Day 2019SystemC Evolution Day

Workshop on the Evolution of SystemC Standards
Colocated with DVCon Europe 2019
Thursday, October 31, 2019 (day after DVCon Europe 2019)
Holiday Inn Munich City, Germany

Find out more >


2019 Global Sponsors

CadenceMentor, a Siemens BusinessSynopsys

Become a sponsor. Sponsorship of events provides many benefits including awareness and targeted lead generation. Interested in becoming a Global Sponsor for 2019? View our Sponsorship Package. If you would like information on sponsoring an event or becoming a global sponsor, please contact us.

Presentations from Past Events

Presentations from many past events are available for download.