Community Newsletter: August 2021
IN THIS ISSUE:
- Message from the Chair
- In-Person Events, New Standards, and Much More!
- News from our Working Groups
- SA-EDI 1.0 Now Available
- SystemC Common Practices Subgroup Call for Contributions
- UVM-AMS Workshop at DVCon Europe
- Upcoming Events
- DVCon Europe 2021
- SystemC Evolution Day 2021
- DVCon India 2021
- DVCon U.S. 2022
- Post-Event Summaries
- ESD Alliance/Accellera Work from Home Panel Series
- SystemC Evolution Fika
- DVCon China 2021
- IEEE Get Program Update
Message from the Chair
As summer comes to a close, I’d like to thank the Accellera working group members for all their hard work the last few months. We’ve held virtual and in-person events, announced new standards, and have much more still to come this fall and winter.
DVCon China was our first in-person event since the pandemic forced the world to quickly pivot and find ways to connect virtually. Congratulations to the Steering Committee for putting on an outstanding conference with record-setting local attendance for the first face-to-face DVCon in over a year.
We are very excited about our newest standard to address security concerns for hardware IP. The Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0 from our IPSA Working Group was released last month. In just a little over three years the initial Proposed Working Group meeting was held, the active IPSA Working Group was formed, and all of the hard work to bring the standard to fruition took place. It’s a remarkable achievement.
This fall our UVM-AMS Working Group will be releasing its whitepaper, and the SystemC Verification Working Group is on track to release its 1.0 standard for public review by the end of the year. As our working groups continue to develop new standards and advance existing standards, we encourage you to get involved and provide feedback to ensure that the standards meet your needs.
With the transition from remote work back to the office continuing to evolve, we co-sponsored a two-part virtual panel series with ESD Alliance that explored the topic. The first panel focused on how engineers worked remotely through the pandemic and continued to be successful, while the second panel took the executive view, focusing on the post-pandemic workplace and what that might look like. The topics are related to most—if not all—of our members, and many were participants in both panels. If you weren’t able to attend the live panels, they are available to view on our website. I encourage you to share your varied work experiences during the pandemic and best practices for success with your companies and colleagues.
I look forward to the industry’s next big event with the Design Automation Conference coming in December. I hope to see you in San Francisco!
With Covid variants remaining a concern, please continue to be vigilant and safe.
Lu Dai, Accellera Systems Initiative Chair
News from our Working Groups
New Security Annotation for Electronic Design Integration Standard Now Available!
The Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0 is now available for immediate download. Developed by the IP Security Assurance (IPSA) Working Group, the new standard defines a specification that documents security concerns for hardware IP and its associated components when integrated into an IC.
With the new standard, IP providers can either identify security concerns to mitigate within their IP or disclose the concerns to their integrator. The standard is design, product, and tool independent. Users of the SA-EDI standard can provide consistent security collateral in a uniform format.
Members of the working group are presenting a 90-minute tutorial “Identifying Security Weaknesses in Electronic Design Using a Standardized methodology” at the upcoming Design Automation Conference (DAC) in San Francisco, CA on December 8, 2021. Live demonstrations will showcase how the SA-EDI standard can be used to identify security concerns when integrating IP. Registration through DAC is required to attend the tutorial.
For more information on the new standard, including a recording of a workshop at virtual DVCon U.S. 2021, visit the IP Security Assurance Working Group page.
SystemC Common Practices Subgroup Call for Contributions for Modeling Registers in SystemC
As a result of the SystemC Evolution Fika panel discussion in June on Model Libraries, the Accellera SystemC Common Practices Subgroup (CPS) would like to collect industry best practices on modeling registers in SystemC. If you have a way to model registers that you would like to share with the rest of the community, we welcome your input. Ideally, the CPS would like to receive a prototype, whether complete or not, that is an example implementation of a register that can be used to define a Register-discovery/Inspection API.
The call for contributions is open through August 31, 2021. Contributions are appreciated in any form, as long as they comply with the Accellera IP Rights Policy.
UVM-AMS Working Group to Hold Workshop During DVCon Europe
The charter of the UVM-AMS Working Group (WG) is to develop a standard that will provide a unified analog/mixed-signal verification methodology based on UVM, with a major focus on transient analysis. During a workshop at DVCon Europe, the UVM-AMS WG will share its findings, requirements, and ideas collected so far, as well as plans for standardization. The following main aspects under consideration for the standard will be discussed during the workshop:
- A UVM-AMS framework for the creation of analog/mixed-signal verification components and testbenches by introducing both extensions to digital centric UVM verification IP classes and related module-based components to facilitate interactions between the class-based and structural environments.
- A set of class-based extensions to UVM related to driver, monitor, scoreboard, etc., to support analog/mixed-signal verification.
- A set of components and/or packages in SystemVerilog and/or Verilog-AMS to facilitate interactions between the class-based and structural environments and to interface with various types of Analog Design Representations.
- A set of Application Programming Interfaces (APIs) to enable the development of modular, scalable, and reusable verification components and testbenches, including stimulus, sequence, and analysis functions, etc.
- A framework for the creation of mixed-signal verification UVM verification components (UVCs) or extensions of existing UVCs for enhanced stimulus, analysis, monitoring, and debug capabilities.
Attendees are encouraged to provide comments, ask questions, and offer suggestions during the workshop. More information on the workshop and the rest of the DVCon Europe program will be available on October 8. For more information on DVCon Europe 2021, including registration, visit the website.
DVCon Europe 2021 Registration is Open!
Mark your calendars! DVCon Europe will be held virtually October 26-27, 2021. Registration is open and advance registration rates are available through September 27. For more information and rates, visit the registration page.
The selection committees for the paper, poster, tutorial, and panel proposals are hard at work evaluating the many excellent submissions to put together another outstanding technical program for attendees. The program will be available October 8, 2021.
To read the welcome letter from Sumit Jha, DVCon Europe 2021 General Chair, visit here.
Recordings of many of the presentations from DVCon Europe 2020 are available on the Accellera Vimeo site.
SystemC Evolution Day 2021
Following DVCon Europe, the sixth annual SystemC Evolution Day will be October 28, 2021. The virtual event is a full-day technical workshop on the evolution of SystemC with the goal to advance and enrich the SystemC language, extensions, and ecosystem. In several in-depth sessions, current and future topics focused on SystemC will be discussed in order to evaluate and accelerate their progress towards further development and adoption among the SystemC community and in Accellera SystemC Working Groups.
The event is intended as a lean, user-centric, hands-on forum bringing together experts across the SystemC user community, industry, and working groups.
For more information and to view past presentations, visit the SystemC Evolution Day page.
DVCon India 2021
Letter from Pradeep Salla, DVCon India 2021 General Chair
On behalf of the Design and Verification Conference (DVCon) India 2021 Steering Committee, it is my pleasure to welcome you all to the sixth edition of DVCon India, planned for December 14-16, 2021 as a virtual conference. We are bringing DVCon India 2021 in a wholistic virtual platform comprised of in-depth technical content over three days. This is an upward shift and progression from the Accellera Day that we organized in 2020. We thank you all and the entire ecosystem for the understanding and cooperation throughout this journey.
The IC industry continues to grow thanks to the Systems, Automotive, and Technology unicorns venturing to design their own chips and well-established IC companies and start-ups bringing in new innovations and chip architectures. While there are a lot of new designs and architectures, we continue to evolve in how we design, verify, and validate theses new architectures, constantly thriving to shift left to shrink our project schedules while ensuring the designs comply with the various standards for safety and security. All I can say is that the excitement continues to surge!
We are witnessing a huge archetype shift in the way we will be working in the post pandemic era, which brings its own challenges and opportunities. The initial plan for 2021 was for a live event, but given the sternness of the second wave of the pandemic in India, we decided to make it a three-day virtual conference.
This year’s edition will have a good mix of Vision and Keynote talks, lively panel discussions, tutorials, and workshops to go with the user papers and posters.
This year’s Steering Committee has members from various companies from the ecosystem, and each committee member brings his or her own experience and expertise to the conference. We also have a very strong Technical Program Committee for this year’s edition. The entire team is working to deliver a world class technical conference.
We invite the entire technical fraternity from the ecosystem to actively participate, share their learnings with the rest of the community and take an active part in DVCon India 2021.
This conference will give you ample opportunities to share and highlight your technical contributions in the areas of Verification & Validation, Methodology & Automation, Functional Safety & Security, Low Power and Mixed Signal Design, Static and Formal Methods, and Digital Twins and SystemC Modelling.
We invite you to join us in this exciting journey and make it a grand success!
For more information on DVCon India 2021, visit the conference website.
The Call for Abstracts for DVCon India 2021 has been extended to August 22.
DVCon U.S. 2022
DVCon U.S. will be held in-person February 28-March 3, 2022 at the Doubletree Hotel in San Jose, California.
“Now in its 34th year, DVCon has become the gathering place for practicing engineers to meet with their peers, share insights and gain valuable, practical knowledge that can be applied to current and future projects,” stated Vanessa Cooper, DVCon U.S. 2022 General Chair. “Our Steering Committee has put together a wide range of suggested topics for our 2022 program and we encourage your submissions to help DVCon U.S. continue to be the industry’s must-attend design and verification technical conference and exhibition.”
The submission site for extended abstracts is open through August 20, 2021. The site for panel, sponsored short workshops and sponsored tutorials is open through September 14, 2021. For more information on suggested topics and guidelines visit the conference website.
To view videos presentations from Accellera working groups during Accellera Day at DVCon U.S. 2021, visit here.
ESD Alliance/Accellera Work from Home Series
The first virtual panel in our series co-sponsored with ESD Alliance, “Remote Work, Remote Chip Design: Building Chips During a Pandemic” was held in June with Ashish Darbari from Axiomise, Mark Glasser of Cerebras, Martin Barnasconi from NXP, Lu Dai of Qualcomm, and Patrick Lynch from Xilinx answering questions posed by moderator Tom Fitzpatrick from Siemens. The panelists discussed the challenges they faced while working from home during the pandemic. It was a lively discussion with many different examples of how the engineers managed their projects remotely over the last 16 months. You can view a recording of the panel here.
Part two of the virtual work-from-home panel series, “The Executive View — Returning to the Office” was moderated by KT Moore, Vice President of Cadence Design Systems, and featured panelists Donna Yasay, Senior Leader, Solutions Architecture at Amazon Web Services (AWS); Vicki Mitchell, Vice President, Systems Engineering of Arm; Amin Shokrollahi, CEO and President at Kandou; and Geoffrey Shippee, Vice President Engineering of Qualcomm. Panelists explored transition strategies, discussed the tradeoffs between remote and in-office work, and shared evolving policies with travel and relocation. Attendees engaged with the panelists during a thought-provoking Q&A toward the end of the session. View a recording of the panel here.
SystemC Evolution Fika Workshop
The second SystemC Evolution Fika was held in June. The two-hour virtual technical workshop had presentations on SystemC and QEMU from GreenSocs as well as a panel focused on SystemC Modeling Libraries. For more information and to view past presentations, visit the SystemC Evolution Fika page.
DVCon China 2021
DVCon China returned in May 2021 with an in-person conference and exhibition. More than 270 people were in attendance for the full-day event in Shanghai, an increase from the previous in-person DVCon China in 2019. Almost half of the attendees were new to DVCon China. There were two keynote presentations, seven paper presentations, 14 short workshops, 12 posters and a tutorial for attendees to choose from throughout the day. Plans are underway for DVCon China 2022 – stay tuned for more information coming soon!
IEEE Get Program Update
Since its inception, the Accellera-sponsored IEEE Get Program has resulted in more than 129,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEEE Standards page on the Accellera website.
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Copyright 2021 Accellera Systems Initiative