Community Newsletter: May 2014



Message from Accellera Systems Initiative Chair

Shishpal Rawat, Accellera Systems Initiative Chair

Many exciting things are happening at Accellera. Due to explosive growth over the last decade, our flagship industry event, the Design and Verification Conference and Exhibition, is expanding to Europe and India. As many of you know, DVCon is a unique user-oriented conference that tackles the technical design and verification issues relevant to your job today as well as the future. The groundswell of regional support and interest in Europe and India is fueling this expansion. This has created new opportunities for Accellera members and our ecosystem to develop new business and partnership opportunities. I invite you to read the blog from Pawan Fangaria of DVCon India detailing the new conference and his excitement to bring the DVCon community to India. Also check out the latest happenings with DVCon Europe including videos from exhibitors expressing the relevance of this event.

Technical tutorials from DVCon United States from the past several years are available on our website. Topics range from SystemC, UVM, IP XACT, OCP, SystemC AMS, Low Power and more. Our latest tutorial, "Experience the Next ~Wave~ of Analog and Digital Signal Processing using SystemC AMS 2.0," is a highly technical tutorial focused on abstract mixed-signal modeling for system-level design and verification. We also recently released "UVM — What's Now and What's Next" in which technical experts share their experiences on pragmatic topics that can be applied to the UVM standard.

At DAC, Accellera will again host our breakfast on Tuesday. A panel of users will discuss UVM 1.2, the move to IEEE standardization and what happens next. We will also present our leadership award to an outstanding contributor to Accellera. In addition, NASCUG (North American SystemC Users Group) will host a meeting on Monday afternoon. 

At Accellera, we are always looking for ways to connect users in the EDA and IP ecosystem with resources to help them thrive and love their jobs. We invite you to join us at an upcoming event. Please also visit our online technical tutorials and communities


Shishpal Rawat, Accellera Systems Initiative Chair
May 2014


Accellera at DAC


North American SystemC User's Group Meeting (NASCUG)

Monday, June 2
1:00-6:00 pm
Room 220, Moscone Center North

Register >

A central component of the half-day user's group meeting is a number of short user experience presentations discussing techniques of design, modeling and verification using SystemC.

Presentation topics:

  • Keynote: Introducing the Universal Verification Methodology (UVM) in SystemC and SystemC AMS
  • An Approach to Verification of Many-Core Systems Using the Software Virtual Platform
  • Out-of-Order Parallel Simulation of SystemC Models using Intel MIC Architecture
  • S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis
  • Reusable Model of AMBA AXI4 Communication Protocol for HLS-based Design Flow

View complete agenda and abstracts >


Accellera Breakfast & Panel Discussion

Tuesday, June 3
Room 220, Moscone Center North

Register >
Pre-registration is required for this free event. Seating is limited, so register early!

Shishpal Rawat, Chair of Accellera, will present an update including progress in the standards development working groups, the successful IEEE GET program, and the development of the Accellera user communities. Shishpal will then present the Accellera Leadership award.

UVM 1.2 Roundtable with John Aynsley
John Aynsley, CTO of Doulos, will engage panelists in a lively discussion of topics including UVM usage, the upcoming UVM 1.2 standard, migration planning, potential future enhancements to UVM, and more. John will also take questions from the audience and have the panelists address those questions. With a good breakfast and a lively discussion you’ll be energized to dive into your busy day at DAC 2014.

Sponsored by:


Birds-of-a-Feather Meeting: Portable Stimulus Proposed Working Group

June 3. 2014
Moscone Center
Check on-site for room location
Pre-registration is not required

This Birds-of-a-Feather meeting will further the work of the new Portable Stimulus Proposed Working Group discussing industry needs in the area of portable stimulus and exploring initial target areas for a portable stimulus standard. The agenda will be to provide a brief summary of the kickoff meeting, followed by an open discussion of general requirements.


Technical Spotlight: Portable Stimulus Proposed Working Group

By Matthew Ballance, organizer

The Accellera Portable Stimulus Proposed Working Group held its kick-off meeting on May 7, 2014 at the Mentor Graphics office in Fremont, CA. This is the first Proposed Working Group set up under the new Accellera policies and procedures. Attendees representing EDA users and vendors presented industry needs in the area of portable stimulus, and discussed potential requirements for a standard. The consensus of the group was that there is perceived value in having a standard in the portable stimulus specification space. It was also clear that the potential problem space is very large, and carefully defining the initial target areas for a portable stimulus standard is key to arriving at a useful standard in a reasonable period of time. Find out more >

Two upcoming events have been scheduled to further the work of the proposed working group. The next regularly-scheduled meeting of the proposed working group will be held on Monday, June 16 via teleconference. A Birds-of-a-Feather meeting will also be held at DAC on Tuesday, June 3 from 7:00 to 8:30pm.

Presentations and meeting notes from this meeting, as well as details for upcoming events and how to join, will be posted on the Portable Stimulus PWG page.


Technical Tutorials from DVCon Available

"Experience the Next ~Wave~ of Analog and Digital Signal Processing using SystemC AMS 2.0" is a multi-part interactive tutorial that targets system engineers, integrators, architects and verification engineers active in industrial projects where analog and digital signal processing functionality comes together and where interoperability between mixed-signal and HW/SW subsystems becomes apparent. The tutorial contains several "labs," so viewers are encouraged to actually create models, run simulations and look at waveforms.

"UVM — What’s Now and What’s Next" is a five-part tutorial for new and experience users. Topics include sequence creation, register layer use (both beginner and advanced), TLM-based communication, test execution using run-time phases, and messaging enhancements.


In the News


New SystemC Core Language and Verification Libraries Available

Two new libraries have been released for the SystemC core language. The SystemC 2.3.1 proof of concept library is an update to the standard that was released in 2011 which included transaction-level modeling. SCV 2.0 contains an implementation of the verification extensions.

Find out more >
Download the standard >

Andy Goodrich Receives Accellera Systems Initiative Technical Excellence Award

Andrew (Andy) Goodrich, a member of the SystemC Language Working Group (LWG), is the recipient of the third annual award. The award recognizes the outstanding achievements Andy made to SystemC standardization, including acting as chief developer of the SystemC Proof-of-Concept simulator

Read the press release >


DVCon India – Start of a new Chapter in Design and Verification Conference

Setting the Standard Blog

By guest blogger Pawan Fangaria, Promotions Committee, DVCon India

It’s time to recollect my memoirs from the year bygone. In April last year I was attending the ISCUG (Indian SystemC User Group) conference. Dennis Brophy, Vice Chairman of Accellera Systems Initiative (which promotes various SystemC User Groups worldwide along with many other verification language and methodology initiatives) provided a great background about various working groups and their activities across the geography. There were other keynote speeches and technical presentations given by industry leaders and several great technical paper presentations from across the world. It was a true conference of international standards; however a need was felt to increase its scope by including all the standards of Accellera which could make it relevant to a wider engineering community involved in design and verification of Electronic Systems & Semiconductor Chips. Late in the evening, I witnessed a great brainstorming session among the steering team members of this conference on how to increase the participation from the semiconductor design community for this conference to uncover its true worth. Umesh Sisodia, ISCUG organising committee chairman, proposed a couple of scenarios and most appealing among them was to make it DVCon India on similar lines as DVCon United States and DVCon Europe.

Today, it’s a delighting pleasure to see this happening. With the generous support from Accellera, the DVCon India conference is becoming a reality. It’s taking its birth this year sometime in September. This will have expanded scope of the burgeoning verification technologies for today’s large SoC designs along with a parallel track on SystemC-related topics such as Virtual Prototyping for Electronic Systems and SoCs, Architectural Exploration, High Level Synthesis, Modeling and more. All in all, it’s the best of all worlds in design and verification at all levels, which can use SystemC (and its variants like SystemC-AMS), SystemVerilog, Verilog along with several methodologies like UVM and OVM protocols like OCP for IP and formats like IP-XACT and many more. Given the wide spectrum of verification technologies such as Assertions (SystemVerilog/SVA, PSL, OVL, etc.), Formal Verification, Emulation, Hardware Acceleration and FPGA prototyping along with the most prominent simulation based verification being used by various design houses, we hope to have a great level of participation from various design teams sharing their view points, success stories and proposed improvements. Since verification of SoCs is ever growing and never complete with one particular methodology, new methodologies and languages are still unveiling. We are here to see these new innovations in verification along with design innovations at platforms based on SystemC, TLM, SystemVerilog and many more. I wish industry leaders, chip designers, system architects, IP developers, SoC integrators, and software and firmware engineers to participate with new vigour in this conference in the vicinity of India and make it successful. As we hear from IESA about the Indian electronics industry growing up to $400B in revenue by 2020, having such a conference in the India region is a step in the right direction to increase sharing of technologies, innovation and best practices among budding engineers, thus creating the value greater than the sum.

DVCon India, sponsored by Accellera Systems Initiative, will have expert technical content covering Electronic System Design & Verification, SoC Design & Verification, Embedded Software, and IP Development & Verification among others. There will be keynote speeches, panel discussions, tracks of technical paper presentations on several topics, poster sessions, and exhibits from EDA, IP and design vendors, tutorials from industry experts and more.

I am excited to witness this conference from its inception and see a large attendance and presentations from the India region along with international participation as we desired during our steering meeting discussion. It’s an opportunity to be availed by the local community in global perspective. Stay tuned for more announcements on DVCon India!!


Upcoming Events


SystemC Japan 2014

June 20, 2014
Shinyokohama, Japan
Seminars / Lunch / Party with Exhibition

DVCon India 2014

DVCon India

September 2014
Bangalore, India

DVCon Europe 2014

DVCon Europe

October 14-15, 2014
Munich, Germany

Sponsorship opportunities available! Brand your company and tools at DVCon Europe!


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