Community Newsletter: August 2023
IN THIS ISSUE:
- Message from the Chair
- New Proposed Working Group
- o Federated Simulation Standard Call for Participation
- Working Group Updates
- IP-XACT Supplemental Material
- SystemC AMS 2.3.4 Regression Suite Released
- New Accellera Repositories at GitHub
- Events Around the Globe
- DVCon Taiwan - September 7
- SystemC Fika - September 12
- DVCon India - September 13-14
- DVCon China - September 20
- DVCon Europe - November 14-15
- SystemC Evolution Day - November 16
- DVCon U.S. - March 4-7, 2024 - Call for Contributions
- Recent Press Coverage
- SemiWiki Covers DAC Lunch Panel Focused on CDC
- IEEE Get Program Update
With summer nearing its end, we are looking forward to a very busy fall at Accellera and with our DVCon conferences around the globe.
We will hold three conferences in Asia next month: DVCon India, DVCon China, and our first ever DVCon Taiwan. I am honored to kick off the new conference with the keynote address and welcome Taiwan into the DVCon community.
In July Accellera sponsored a lunch panel during the 60th Design Automation Conference (DAC) focused on tackling SoC integration challenges. It was a great success with a very engaging discussion among our panelists. During the luncheon we also announced an upcoming federated simulation exploratory meeting. The meeting was held shortly after DAC, with many interested parties coming together to discuss and assess the industry need for a simulation integration standard across multiple platforms. As a result of significant interest, we’ve since formed the Federated Simulation Standard Proposed Working Group, with the first meeting in France at the end of next month.
We’ve seen a great deal of activity in our working groups over the summer. The IP-XACT Working Group released supplemental material for the latest IEEE 1685-2022 version including vendor extensions, release notes, and much more. The SystemC AMS team just released its 2.3.4 regression suite, and the SystemC CCI Working Group recently released reference implementation 1.0.1. Also on the horizon is the SystemC reference implementation based on the just approved IEEE 1666-2023, as well as Portable Stimulus Standard 2.1 that will include several new features.
We are always open to input on what should be standardized or new ideas to improve an existing implementation. Do you have an idea for a standard or tip you’d like to share? We invite you to join our online forums and begin a discussion. Our standards and reference materials are of great value because of the tremendous collective knowledge and contributions from our community.
In addition to our standards offerings, our membership also continues to grow. We’ve added seven new members so far this year. I’d like to take this opportunity to welcome our newest Accellera member, SiFive, a leader in RISC-V implementation.
Other activities this fall include our virtual SystemC Evolution Fika workshop in September and DVCon Europe and SystemC Evolution Day in November.
I hope to see you at one of our conferences soon.
Lu Dai, Accellera Systems Initiative Chair
Accellera recently announced the formation of a Federated Simulation Standard Proposed Working Group (PWG) to focus on the creation of a distributed and orchestrated multi-domain simulation framework.
“A group of Accellera members have been part of a larger exploratory team looking at cross-industry collaboration to exchange knowledge and best practices,” stated Lu Dai, Chair of Accellera. “The team has been investigating the coordination of efforts in standards development and the integration of simulation technologies. The objective of the PWG is to identify industry interest and consolidate the requirements to drive standardization and development of an open API and federated simulation ecosystem. We encourage all interested companies to join the PWG and provide input on the need for a standard in this area.”
“The intent of the proposed Federated Simulation Standard (FSS) is to facilitate the creation of a distributed and orchestrated multi-domain simulation framework, compatible with and complementary to existing approaches used in different industries and sectors,” stated Martin Barnasconi, Accellera Technical Committee Chair and Chair of the PWG. “A standardized communication interface will enable interoperability of virtual modeling, simulation, and integration throughout the product lifecycle. In parallel to the efforts of the PWG, we target establishing an industry-funded project under definition by the Institute for Research and Technology (IRT) Saint Exupéry in Toulouse, France. We look forward to the input from the industry during this initial standardization phase.”
The first PWG meeting will be held over two days in Toulouse, France. On Monday, September 25 attendees are invited to present use cases, requirements, and expectations of the standard. Tuesday, September 26 will focus on the organizational aspects and intended alignment with other project initiatives or organizations, such as IRT Saint-Exupery, Eclipse Foundation, Linaro, etc. The meeting location and time will be communicated when registering to attend this event.
Participants in the FSS PWG do not need to be from Accellera member companies. If you are an Accellera member, you can join the PWG here (login required). If you are not an Accellera member and would like to participate in the PWG, submit your information here.
To attend the first PWG meeting in Toulouse, participants are invited to register here. If you are unable to attend the meeting in person, teleconferencing facilities will be offered for some parts of the meeting. More information on this will be communicated to the registered PWG members in early September.
Companies that have shown initial interest include Airbus, AMD, Aptiv, AVL, Bosch, Cadence, Collins Aerospace, IRT Saint-Exupery, NXP, Qualcomm, Shokubai, and Spacebel.
For more information about the PWG and first meeting, visit here.
Update to IP-XACT Supplemental Material Now Available
IP-XACT supplemental material aligned with IEEE 1685-2022 has been released. Updates include:
- XML Schema Definition files reflecting the IEEE 1685-2022 standard.
- XML Schema Definition files reflecting the Accellera Vendor Extensions for 1685-2022.
- Accellera Recommended Vendor Extensions for 1685-2022. Please see the description here.
- Accellera scripts to convert 1685-2014 IP-XACT XML files to 1685-2022 XML files.
- Release notes that describe the differences between 1685-2014 and 1685-2022.
- Document of issues found for 1685-2022 that need to be addressed in a future version of the standard.
The working group is planning to publish an update to the IP-XACT User Guide aligned with 1685-2022 next month.
Two IP-XACT focused tutorials will be presented during DVCon Europe in November. One tutorial will cover new material available in the user guide. The other tutorial will have representatives from Agnisys, Arteris, Infineon, and Intel present how they use the standard. More information will be available when the DVCon Europe 2023 program is released.
For more information on IP-XACT, visit the working group page.
SystemC AMS 2.3.4 Regression Test Suite Released
The SystemC AMS Working Group has released its test suite to enable validation of implementations and tools against the SystemC-AMS language standard IEEE Std 1666.1-2016.The test suite contains more than 700 tests, covering both unit-level and application-level tests. It supports the latest implementation of the SystemC AMS proof-of-concept implementation version 2.3.4.
The SystemC AMS regression test suite and the SystemC AMS proof-of-concept implementation are available for download.
New Accellera Repositories at GitHub
To enhance the interaction with the Accellera community and enable seamless integration with community-driven build-flows, Accellera has released new public repositories under its GitHub account.
The Universal Verification Methodology (UVM) Working Group released the UVM repository, providing a SystemVerilog library matching the requirements of IEEE Std 1800.2-2020. This public repository is typically updated only together with public releases of the Accellera UVM reference implementation. In between public releases, bug fixes may be published via the public repositories as well.
You can find all Accellera public repositories here: https://github.com/accellera-official
The first DVCon Taiwan will be held September 7th in Hsinchu. There will be four morning keynotes with Lu Dai, Accellera Chair and Senior Director, Qualcomm, presenting the opening keynote, “Accellera, Standards and the Semiconductor Supply Chain.” Dr. Paul Cunningham, Senior Vice President and General Manager, Cadence will present the second keynote, “Next Generation EDA – Leveraging AI to Achieve the Next 10x.” The third will be “Autonomous Verification: Are We There Yet?” presented by Ajay Singh, Senior Vice President, Synopsys. Abhi Kolpekwar, Vice President and General Manager of Digital Verification Technologies, Siemens EDA rounds out the morning keynote presentations with “Smart Verification: Faster Is Not Enough!”
A panel, “How to Develop Future Talents in Design Verification,” concludes the morning sessions. Attendees will have 14 technical papers to choose from throughout the afternoon.
For more information and to register, visit the DVCon Taiwan 2023 website.
SystemC Evolution Fika
The next SystemC Evolution Fika will be held September 12. The virtual workshops are referred to as Fikas to honor the Swedish tradition of sharing a coffee, slowing down a bit, and talking about things the participants care about.
There will be three presentations followed by an open discussion and look forward:
- “SystemC IEEE 1666 Update,” will be presented by Jerome Cornet, ST Microelectronics and IEEE P1666 Chair. The presentation will focus on some of the features of the upcoming revision that modernize the language and enable new use cases.
- “Tracing in SystemC” will focus on establishing a standardized approach to capture and store simulation data and will be presented by Lukas Jünger, MachineWare GmbH and Eyck Jentzsch, Rocco Jonack, MINRES Technologies.
- Andy Goodrich, Accellera Allied Member, will present, “SystemC Data Types.” The presentation will describe the changes made to the rewrite of the SystemC arbitrary-width integer support to improve performance. The presentation will also provide some benchmark results.
To register for the free SystemC Fika, visit here.
For more information and to view presentations from past fikas, visit the SystemC events page.
The eighth annual DVCon India will be held September 13-14 at the Radisson Blu in Bangalore. A packed two-day technical program is in store for attendees. There are six keynotes on high-level industry topics; eight workshops, including one presented by Accellera Chair, Lu Dai; two panels; poster sessions; a vision talk; and numerous tutorials to choose from. Attendees can also look forward to many network opportunities throughout the conference, as well as an exhibition to see the latest products available for the practicing design and verification engineer.
For the full program and to register, visit the conference website.
For proceedings from past DVCon India conferences, visit here.
- “CEDA 2.0 – Leveraging AI to Achieve the Next 10X” will be presented by Yogesh Goel, Cadence.
- “System Design with Agile Verification and Continuous Acceleration” will be presented by Felix Cha, XEPIC.
In addition to the keynotes, attendees can look forward to 12 papers, nine short workshops, two tutorials and a full-day exhibition. For more information on DVCon China, including a QR Code to follow the conference and exhibition on WeChat, visit the conference website. Registration information is available here.
Keynote presentations will be provided by:
- Philippe Notton, CEO & Founder SiPearl: “Energy-efficient High-Performance Compute, at the Heart of Europe”
- Michaela Blott, Senior Fellow at AMD Research: “Pervasive and Sustainable AI with Adaptive Computing”
New to DVCon Europe 2023 is a research track. Authors were solicited from universities and research institutes to contribute high quality research papers. Papers chosen for the DVCon program will be published following the conference as academic papers.
To register visit here.
For proceedings from past DVCon Europe conferences, visit here.
SystemC Evolution Day
Co-located with DVCon Europe, the eighth annual SystemC Evolution Day will be held November 16 from 9:00-17:00 CEST at the Holiday Inn Munich City Centre.
SystemC Evolution Day is a full-day technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. It is intended as a lean, user-centric, hands-on forum bringing together experts from the SystemC user community and the Accellera working groups to advance SystemC standards.
For more information on SystemC Evolution Day and other SystemC events, visit the SystemC Events website.
Presentations and videos from SystemC Evolution Day 2022 can be found here.
DVCon U.S. 2024 Call for Contributions Is Open!
The 36th annual DVCon U.S. will be held March 4-7, 2024, at the Doubletree Hotel in San Jose, California. The call for contributions for extended abstracts, panels, sponsored short workshops, and tutorials is open.
“Our Technical Program Committee is looking forward to putting together an exciting and informative program for DVCon U.S. 2024 attendees,” stated Tom Fitzpatrick, DVCon U.S. 2024 General Chair. “We welcome your proposals focused on your challenges, experiences, and use of standards and new technology. I’d like to point out that this year is a little different as far as submission deadlines are concerned. This year we’ve added more time after the summer break before abstracts are due, so we won’t be extending the submission deadline past September 15th. Submitting an abstract is a great opportunity to be a part of the industry’s must-attend conference for practicing engineers,” Fitzpatrick concluded.
More information and guidelines for extended abstracts, due September 15 can be found here.
Guidelines and suggested topics for sponsored tutorials and workshops can be found here.
The deadline to submit an abstract for a thought-provoking panel is October 2. More information and guidelines can be found here.
The proceedings from DVCon U.S. 2023 are available to view on demand.
Daniel Payne, editor for SemiWiki, attended Accellera’s luncheon and panel at the Design Automation Conference in July. His coverage of our panel, “Tackling SoC Integration Challenges,” highlights the efforts of Accellera’s Clock Domain Crossing Working Group. Read the full article here.
Since its inception, the Accellera-sponsored IEEE Get Program has resulted in over 170,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEEE Standards page on the Accellera website.
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