Community Newsletter: December 2012

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Message from Accellera Systems Initiative Chair

Shishpal Rawat, Accellera Systems Initiative ChairSeason's Greetings from Accellera Systems Initiative! It's been one year since Accellera and Open SystemC Initiative merged to become Accellera Systems Initiative. We have had a terrific 2012, and I'd like to share with you some of the highlights and accomplishments from this year:

  • Completion of the new SystemC open source proof-of-concept library including support for transaction-level modeling. Version 2.3.0 is compatible with the IEEE 1666 standard and available for free download.
  • Completion of the Unified Coverage Interoperability Standard (UCIS), a first step towards the interoperability of verification coverage data across multiple tools from multiple vendors. The specification of UCIS 1.0 is available for free download.
  • Completion of the SystemC AMS 2.0 draft standard to advance dynamic and reactive mixed-signal system design. The draft of the LRM is available for free download.
  • Attendance at our 2012 Design and Verification Conference (DVCon) increased 10%, and tutorial attendance was up more than 50% from 2011.
  • The first Accellera Systems Initiative Day was held at DVCon and featured tutorials on EDA and IP standards.
  • Full-length tutorials from DVCon are available for free download. This is your number one resource to find the latest in standards including SystemC, UVM, UCIS and IP-XACT.
  • John Aynsley was honored with our Technical Achievement Award for his outstanding contributions to the SystemC standard.
  • Accellera received the Tenzing Norgay Interoperability Achievement Award from Synopsys for advancing industry standards that enable interoperable system design flows.
  • Vice chairman Dennis Brophy was honored with our first-ever leadership award.
  • We sponsored several industry events and user meetings in the US, Europe, India and Asia.

As we look ahead to 2013, we have some exciting work ahead in standards. Stay tuned for information on the upcoming release of IEEE-1800 System Verilog, plans for UVM 1.2, continued progress on SystemC, and contributions on SystemRDL.

On behalf of all of us at Accellera Systems Initiative, I wish you a healthy and happy holiday season.  If you have any comments or suggestions for us, we welcome you to contact us. We look forward to 2013 as we get ready for another excellent year in standards innovations.


Shishpal Rawat, Accellera Systems Initiative Chair
December 2012


Technical Committee Spotlight: Global Standards

Accellera not only gives birth to new standards but helps to assure their proliferation worldwide. Stan Krolikoski, Accellera Systems Initiative Secretary and IEEE Design Automation Standards Committee Chair, reports on his November 2012 meeting with JEITA (Japan Electronics and Information Technology Association) to discuss proliferation of EDA standards in Japan.

On November 15, I, in my role as Chair of the IEEE Design Automation Standards Committee (DASC), and Dennis Brophy, in his role as co-convener of the International Electrotechnical Commission (IEC) Working Group (TC91 WG13) that handles EDA standards, met in Yokohama Japan with representatives of the JEITA EDA Technical Committee (henceforth, the "EDA-TC").

JEITA, (the Japan Electronics and Information Technology Association), is comprised of multiple boards (e.g., a Consumer Electronics Board, a Display Devices Board and a Semiconductor Board, among others) that are staffed by representatives from the largest electronics companies and universities in Japan. The EDA-TC, which falls under the JEITA Semiconductor Board, has members from Fujitsu, Sony, Panasonic, Renesas Electronics, Toshiba, Canon, Zuken, Denso, Cadence KK, Nihon Synopsys, NEC, Mentor Graphics Japan and Ricoh, along with Osaka and Kinki Universities. Its structure is seen below:

Activities of the JEITA EDA-TC

With regard to standards representation, the EDA-TC closely tracks EDA standards of interest, especially IEEE DASC standards—including several that were originally developed by Accellera Systems Initiative. For example, when I chaired the P1666 (SystemC) WG in 2009-2010, we received a considerable amount of feedback from EDA-TC members, and several of them attended our WG meetings even though those meetings took place in the middle of the night in Japan. The EDA-TC similarly closely followed the progress of the recently approved IEEE P1800-2012 (SystemVerilog) standard and the P1801 (UPF) standard currently under revision. Furthermore, as a member of the IEEE Standards Association, the EDA-TC also joined the Ballot Group for each of these standards.

The EDA-TC also develops its own EDA standards. For example, in March 2012 they created a LSI-PKG-Board Co-design standard and are now seeking a way to turn this into an international standard. Previously they developed the "Bird’s-eye View of Design Languages (BVDL)," a high-level view of the purposes and relationships between various design and verification languages. The BVDL is on course to become an IEC standard.

In addition, the EDA-TC is currently working on a Nano-Scale Physical Design standard. The working group for this nascent standard has been addressing advanced technology-related issues including process variation, double patterning and so forth. They believe that statistical parasitic information may be a promising candidate for standardization.

Finally, the EDA-TC not only tracks various EDA standards and creates several of its own, but it also helps organize events that help promote both EDA standards and the tools that implement them. For example, it organizes the Electronic Design and Solutions Fair (EDSFair) held every year in Yokohama and the System Design Forum, a smaller but focused event that tackles issues related to system design in an in-depth manner.

During our meeting, the EDA-TC representatives gave a report on their activities to me, Dennis and other DASC members who participated via a conference call. In turn, Karen Pieper and Neil Korpusik (Chair and Vice-Chair of the IEEE SystemVerilog WG) gave a recap of the work that their group successfully completed in developing the 1800-2012 standard. Next, I presented a report prepared by John Biggs, Chair of the P1801 UPF WG. This report focused on the recently completed first ballot of what is hoped will be the 1801-2013 standard. The EDA-TC has closely followed the IEEE UPF work and has attached several comments to their vote that they would like to see resolved.

Finally, Satoshi Kojima, the other co-convener (with Dennis Brophy) of the TC91 WG13 group that handles EDA standards in the IEC, gave an update on the status of the various IEEE DASC standards that either have or are on the way to obtaining "dual logo" (IEEE and IEC) status. To see the importance of dual logo status, first note that while the IEEE Standards Associations are comprised of individuals and "entities" (companies, non-profit organizations, universities, etc.), the IEC WGs are made up of representative countries (U.S., Japan, China, Germany, etc.). Because of this, many National Standards organizations put a premium on standards that come from the IEC rather than the IEEE. Thus, having IEEE standards also become IEC standards—obtaining dual logo status—is very important to the international proliferation of such standards. I was pleased that Kojima-san reported excellent progress regarding the development of several IEEE DASC standards to such status.


On the Road to DVCon 2013

DVCon 2013 tutorial chair Yatin Trivedi gives the scoop on this year's program to be held February 25-28, 2013 in San Jose, CA.

On the Road to DVCon 2013

Find out more about DVCon >


Nominations Open for Accellera's Technical Excellence Award

Calling all users: It's time to honor your peers for their contributions to standards!

Nominations are being held through January 18 for the 2013 Technical Excellence Award. The award recognizes outstanding contributions in the creation of EDA and IP standards by a member of an Accellera technical committee. Any individual who is a member of an Accellera technical committee is eligible to receive the award. Candidates may be nominated by the industry at large and are endorsed by Accellera committee members.

Read more >

Nominate a candidate >


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Resource Corner

Tutorials from 2012 Design and Verification Conference
Tutorials from DVCon 2012 are available for free download on our video site

Special Issue on EDA Industry Standards from IEEE's Design and Test
Download articles for free or nominal fee


Thanks to our 2012 Global Sponsors
for their support of video tutorial production




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